The present invention relates to an improved memory device providing a faster read access time. MOS semiconductor memory devices of various types, such as random access memories (RAMs), read-only memories (ROMs), programmable read-only memories (PROMs), erasable programmable read-only memories (EPROMs), electrically erasable programmable read-only memories (EEPROMs) and first-in, first-out memories (FIFOs) are all well known in the art. Data is stored in these memories during a "write" cycle, and that data is subsequently read during a "read" cycle. These memories are typically used in computers such as desk and lap top personal computers, as well as many other industrial applications. As the chip technology improves, and central processing units (CPUs) become available with higher and higher processing speeds, the time it takes to read data from the semiconductor memories becomes a critical factor in the system. It is desirable to keep this read time, called an "access time" to a minimum.
Reading and writing into a semiconductor memory is usually done through a "bitline". As semiconductor technology has improved, semiconductor memories have gotten denser and denser. At the present time, most dynamic RAMs used in personal computers contain approximately one million bits, and are thus called "one megabit" dynamic RAMs (or DRAMs). The current generation of static RAMs (SRAMs) contain approximately 64,000 or 256,000 bits, and are called 64K SRAMs or 256K SRAMs, respectively. ROMs and EPROMs are also available commercially in 256K and 1 megabit densities.
When semiconductor memories are read, a technique commonly employed is to precharge the bitlines. That means the bitlines are brought up to a particular precharge voltage so that a predetermined amount of charge appears on a bitline which is to be read. As these arrays get denser and denser, there are more and more individual memory cells on a single bitline. This causes the total bitline capacitance to become quite large, for example, one picofarad or more.
It therefore becomes very important during reading that the power supply voltage, the difference between the positive power supply V.sub.cc, typically 5 volts, and the negative power supply V.sub.ss, typically ground, remain constant at 5 volts. If there is a voltage spike causing V.sub.cc to rise somewhat (commonly called a voltage bump), and the ground voltage doesn't rise simultaneously, the power supply voltage becomes greater than 5 volts. Obviously if the ground voltage (called a ground "bounce") also rises in tandem with V.sub.cc, there is no problem since the differential between the positive power supply terminal V.sub.cc and the negative power supply terminal V.sub.ss will still remain at 5 volts. However, when these two phenomenon do not occur simultaneously, and only V.sub.cc is bumped, charge can become trapped onto the bitlines as a result of this higher power supply voltage.
This additional charge causes a problem during a read operation when two bitlines are compared. The selected bitline is pulled down and is compared with another which remains high. If the excess charge isn't removed, on the bitline which is pulled down, reading cannot take place and is delayed. This excess charge must be eliminated before the voltages on the two bitlines will be sufficiently separated for reading to take place.
The conventional apparatus used to read a semiconductor memory will delay a read operation until the relative charge on the selected bitline compared to another is in the predetermined correct range. However, while the reading apparatus is waiting for the trapped charge to dissipate, the read operation will be delayed and a penalty paid in access time--a very important device parameter.
During precharge, the selected bitline is typically pulled to V.sub.cc - V.sub.t. If there is excess charge on this bitline, it is pulled to a higher voltage than necessary. Before the read apparatus will do a read and obtain valid data, there must be a predetermined delta, for example about 60 millivolts, between the bitlines. Excess charge on the bitlines will result in a delay in creating this predetermined voltage difference, and therefore, a delay in the read access time. If the correct voltage differential does not exist, the read apparatus delays the read.
To speed the dissipation of this excess charge on the selected bitlines, prior art techniques employ an "active leaker" transistor. Such a leaker transistor is tied between the bitline and ground. Where there is excess charge on the bitline, the charge leaks off through this active leaker transistor which is always turned on. Once the excess charge has leaked, the bitline can be read.
The problem with this prior art solution is that maintaining the active leaker transistor always in the on condition causes a continuous power drain on the circuit, often several milliamps. For example, in a memory circuit with eight input-output lines, there must be two leaker transistors for each input-output, one for the "true" line and one for the "complement" line. In "split array" architectures with nine input/output lines, thirty-six leakers are commonly employed, eighteen for the left half array and eighteen for the right half array. It is easy to understand that this places a tremendous power drain on the circuit. Since many of these circuits are used in portable applications, power drain is extremely undesirable because battery requirements, and thus weight goes up in proportion to the amount of power required by the memory circuits.
One approach for getting rid of this power drain from the leaker transistors uses a clocking circuit to only turn on the leaker transistors when they were necessary during a read cycle. The problem with this solution is that very precise clock timing is required, and the design of a clock with the requisite precision is difficult. If the clock timing is cut too close, access time will be delayed because the leaker will be turned off too soon before all of the necessary charge has been dissipated. If the clock cycle is made too wide the leaker remains on too long and too much power is burned.
The inventors of the subject invention discovered that a clamp circuit could be used in place of a leaker transistor to dissipate the excess bitline charge. The clamp circuit is an MOS transistor having its gate tied to a source of clamping voltage and its source-drain circuit in series with the bitline and ground. The advantage of this clamp circuit is that it is only turned on by the existence of excess charge in the bitline, and otherwise it remains off. Accordingly, there is no power drain in the bitline circuits except when charge trapping occurs, which is precisely when the clamp is necessary. In the absence of excess bitline charge, the clamp circuit always remains off.
Prior to this invention, a clamp circuit was considered an undesirable solution. In the memory circuits used in the preferred embodiment of the invention, each clamp circuit uses two transistors, and there must be one clamp circuit on each input-output line in the same manner as a leaker transistor had been employed in the prior art. Accordingly, this meant that bitline charge dissipation would require twice as many transistors as had been required using the prior art leaker solution, causing a penalty in chip area. Therefore, the clock solution, which would take far fewer transistors because all of the leakers (for example 36) could be clocked with the same clock devices, was considered a better solution.